Viya Vijayan

Viya Vijayan
Bangalore, Karnataka, India
+22

Profile Snapshot

Viya is based out of Bangalore & has studied VLSI Design and Embedded Systems, ME MTech-Master of Engineering or Technology from Year 2012-2014 in SJCET-St Joseph College of Engineering and Technology, Mahatma Gandhi University.

Viya Vijayan is Skilled in Aptitude

About

I am just completed my internship from maven silicon ( a VLSI training institution in Bangalore) searching for a good opening in my career.
My brief professional profile:
Total experience : 1.5 year (internship)
Current company : Maven silicon ,Bangalore,3.5 months internship experience in VLSI design and verification domain.
Previous company: Network Systems and technologies (P) Ltd,Techno park,Trivandrum, ,1.1 year internship experience in VLSI design domain

Talents

- Aptitude
  
  yRank In Bangalore
  
  yRank In Bangalore
- » Compliment
  
  Global yRank

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Work Experience

Intern

maven silicon

Internships Sep-2015 To Dec-2015 3 months

intern

maven silicon

Internships Sep-2015 To Dec-2015 3 months

Project trainee

Network systems and technologies (p) ltd

Internships Jul-2013 To Aug-2014 1 year 1 month

» 3 Projects

AXI UVC - AMBA AXI4 Protocol Verification

Oct-2015 to Dec-2015

HVL: System Verilog
TB Methodology: UVM
EDA Tools: Rivera-PRO
The AMBA AXI protocol is targeted at high-performance, high-frequency system and includes a number of features that make it suitable for a high-speed submicron interconnects. AXI UVC is a configurable UVM based verification IP.
Responsibilities:
? Architected the class based verification environment in UVM
? Verified the protocol with single master single slave environment
? Verified the UVC by connecting maters and slave back to back

Design of Physical Coding Sublayer (PCS)

Sep-2015 to Oct-2015

HDL:Verilog HDL
Tool Used:Xilinx ISE
Physical Coding Sublayer(PCS) interface is the Gigabit Media Independent Media(GMII) that provides a uniform interface to the reconciliation sublayer for all 1000 Mb/s PHY implementation. In PCS 8 bit data packet is received from MAC layer and this packet is encoded to 10 bit code group and routed to PMA layer and from PMA the 10 bit data packet is decoded to 8 bit data and routed to MAC layer. PCS is working at 125 MHZ. It is a part of Ethernet protocol.
Responsibilities:
? Designed RTL using Verilog
? Verified the design in Verilog environment

AHB2APB Bridge IP Core Verification

Jul-2015 to Aug-2015

HVL: System Verilog
TB Methodology: UVM
EDA Tool: QuestaSim The AHB to APB Bridge is an AHB slave which works as an interface between the high speed AHB and the low performance APB buses.
Responsibilities:
? Architected the class based verification environment in UVM
? Verified the RTL module with single master and single slave
? Generated functional and code coverage for the RTL verification sign-off

Education

Master of Engineering or Technology

St Joseph College of Engineering and TechnologyMahatma Gandhi University

2012-2014 Score80%

Bachelor of Engineering or Technology

ILAHIA College of Engineering and TechnologyAPJ Abdul Kalam Technological University

2008-2012 Score74%

Profile Snapshot

Viya Vijayan is Skilled in Aptitude

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