Raghavendra K S

Senior Physical Design Engineer
Bangalore, Karnataka, India
Aptitude, Verilog, VHDL VHSIC Hardware Description Language
About
B.E, Diploma in Electronics with 4.5+ years of Experience in VLSI was industry.
Talents
Work Experience
Senior Physical Design Engineer
Synapse Pvt Ltd, Bangalore
Full Time Apr-2019 To present 6 years
Responsibilities
  • PNR, Timing Clean, ECO and Sign off with PV clean
Achievements
  • 7nm project
HW - Physical Design Engineer
Full Time Jun-2018 To Apr-2019 10 months
Responsibilities
  • PNR, Timing clean, ECO and sign off with PV clean
Achievements
  • 10 nm project
Design and Application Engineer
Full Time Mar-2016 To Jun-2018 2 years 3 months
Responsibilities
  • Design engineer
Trainee Engineer
SIERRA SOFTWARE DESIGN CENTRE PVT. LTD. (A Division of SIERRA CIRCUITS) - Bangalore, India.
Full Time Aug-2014 To Nov-2015 1 year 3 months
Responsibilities
  • Design verification Engineer
Education
Bachelor of Engineering or Technology
R V College of EngineeringVishweshwaraiah Technological University
2011-2014 Score77%
Diploma in Electronics and Communication
DACG Government PolytechnicDepartment of Technical Education
2008-2011 Score87%
Extra-Curricular Interests

  • Participation in social welfare programs: Blood donation. Gymnastics

  • Badminton

  • Swimming

  • listening to music

  • Playing Cricket

  • watching movies & Internet surfing.

yKnown
Profile Snapshot
Raghavendra is based out of Bangalore & has studied ECE ENTC-Electronics and Tele-Communication Engineering, BE BTech-Bachelor of Engineering or Technology from Year 2011-2014 in RVCE-R V College of Engineering, Vishweshwaraiah Technological University.
Raghavendra K S is Skilled in Aptitude, Verilog, VHDL VHSIC Hardware Description Language and other talents.