Arshabha Arya

Arshabha Arya
B.Tech In Electronics And Communications Engineering (Ece)
Delhi, Delhi, India
Microprocessor, Embedded Systems, Aptitude +22

Profile Snapshot

Arshabha is based out of Delhi & has studied ECE ENTC-Electronics and Tele-Communication Engineering, BE BTech-Bachelor of Engineering or Technology from Year 2013-2017 in GLAU-GLA University, GLA University.

Arshabha Arya is Skilled in Microprocessor, Embedded Systems, Aptitude and other talents.

About

I am good Team Player."works enthusiastically. I have enough motivation for myself and my department. I love what I do, and it’s contagious.”

Talents

- Telecommunications
  
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  98.54 %
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  98.54
- VLSI
  
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  Global yRank
  
  89.6 %
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  89.6
- Embedded Systems
  
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  Global yRank
  
  99.44 %
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- Network Engineer
  
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  Global yRank
  
  42.5 %
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  50

Complete Talent Profile »

Work Experience

Web Developer

Full Time May-2017 To present 7 years 11 months

» 2 Projects

An Ultra-Wideband CMOS Low Noise Amplifier using cascade and cascode topology for 3-5GHz Frequency

Student at GLAU-GLA University

Jun-2016 to Jun-2017

This project deals with the design of a low noise amplifier for ultra wideband (UWB) frequency range from 3-5 GHz considered various parameters which affects its performance and efficiency of subsequent devices that follows. It helps to choose the optimum parameter and choice of different topologies and techniques. This will lead to better gain, noise figure, power consumption etc. The report consists of all the information about the parameter involved the design low noise amplifier. Also, I have specified the values and conditions under which each of the components works. All the parameters value has been tabulated and appropriate graphs have been shown. In this project, I have simulated the proposed circuits on Advanced Design System (ADS) tool and achieved better values for gain and noise figure with low power consumption. The scope of our project is to: Minimum noise figure and enhance gain.

VHDL Implementation of 8-Bit ALU

Student at GLAU-GLA University

Feb-2016 to Jul-2016

This paper primarily deals with the construction of Arithmetic Logic Unit (ALU) using Hardware Description Language (HDL). The design was implemented using VHDL Xilinx Synthesis tool ISE 14.2 and targeted for Spartan device. ALU was designed to perform arithmetic operations such as addition and subtraction using 8-bit fast adder, logical operations such as AND, OR, XOR and NOT operations, 1’s and 2’s complement operations and compare. ALU consist of two input registers to hold the data during operation, one output register to hold the result of operation, 8-bit fast adder with 2’s complement circuit to perform subtraction and logic gates to perform logical operation. The maximum propagation delay is 13.588ns and power dissipation is 38mW. The ALU was designed for controller used in network interface card.